Store Clock and Store Clock Fast Instruction Execution

ABSTRACT

Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation of U.S. patent application Ser. No. 11/532,177 “Enhanced Store Facility List System and Operation” filed Sep. 15, 2006 and assigned to IBM®. The disclosure of the forgoing application is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a computer processing system, and more particularly to executing machine instructions for determining current Time Of Day clock time.

BACKGROUND OF THE INVENTION

Information processing systems include not only general purpose computers which can be programmed to perform tasks of virtually unlimited variety, but also more specialized equipment which typically is employed to perform certain specialized tasks such as information storage and retrieval, media recording and reproduction, etc.

Information processing systems, both general purpose and special purpose systems, typically are enabled to perform specialized tasks by programs. Application programs include those which are adapted especially for a particular end use of an information processing system. Application programs tend to use the resources of an information processing system in ways that can vary greatly from one application program to another. Sometimes, an application program utilizes particular facilities of an information processing system that are infrequently used by other application programs. By way of example, particular facilities used by an application program can include the ability to execute certain instructions that address the needs of the particular application program.

Since particular facilities used by one application program may be infrequently used by other application programs, the facilities need not be included in or be available as part of every information processing system on which other application programs are executed. In some cases, a particular facility is only available when the information processing system is an upgraded version in relation to another less equipped version of the information processing system, e.g., a base model. Alternatively, the particular facility may only be present when the information processing system is specifically configured to incorporate such facility.

Since the facilities available on any given information processing system can vary, it is useful for programs which are executed thereon to be able to determine quickly which facilities of the information processing system are available. Programs can then be executed in a way that takes advantage of the available facilities.

In a prior art information processing system according to the z/Architecture® Principles of Operation (Publication Number SA22-7831-04, available from IBM® Corporation, Armonk, N.Y., which is incorporated herein by reference in its entirety), an instruction known as STORE FACILITY LIST (“STFL”) returns a result which indicates whether or not certain facilities are available and installed on the information processing system. The results are returned in form of a fixed length and fixed definition data record in which each bit thereof identifies whether or not a particular facility is installed. The STFL instruction is also limited in how it can be issued and how the result can be accessed.

One limitation is that STFL is a control instruction. The STFL instruction can only be issued by a program that is being executed in the “supervisor state”. Such program is referred to as a system-control program, or operating system. The STFL instruction cannot be executed by an application program, i.e., a program that is currently being executed in the “problem state,” as opposed to the supervisor state. If the STFL instruction is issued by an application program, a privileged-operation program exception condition is recognized, which prevents the instruction from being executed.

Another limitation relates to the location at which the results returned by the STFL instruction are stored. In accordance with prior art z/Architecture, results returned by the STFL instruction are always mapped to the same real address of 200 (C8 hexadecimal) in memory. Using the z/OS® operating system, this real address is mapped to a real page-frame address of zero in the address space of each application program. In this way, each application program on a system which uses the z/OS® operating system can directly access the result returned by a STFL instruction issued by the operating system. However, when a different operating system is provided such as Linux®, real address 200 is not mapped to a location within the address space of an application program. In that case, an application program cannot view the facilities information returned by the STFL instruction without the support of the operating system (for example, the operating system may provide a system call which will return this information to the application program).

Other limitations of the STFL instruction are the short, fixed length of 32 bits of the result it returns and the fixed definition given to each of the 32 bits included in the result. In certain cases, a particular application program needs to obtain information about the capabilities of the information processing system which does not fit within the traditional bit definitions of the result of the STFL instruction. The number of bits returned by executing the STFL instruction and the definition given to each bit can fall short of the information needed by a particular application program.

SUMMARY OF THE INVENTION

In an embodiment, the present invention provides for executing instructions for storing a value of a time-of-day (TOD) clock, comprising obtaining a first instruction for execution by a Central Processing Unit (CPU) of one or more CPUs in the system; and initiating execution of the obtained first instruction while the TOD clock is incrementing in a set state, the execution of the first instruction comprising

obtaining a first TOD clock value; and storing the first TOD clock value in storage; a second instruction is obtained for execution by a CPU of the one or more CPUs in the system; and subsequent to the initiating execution of the first instruction, execution of the obtained second instruction is initiated while the TOD clock is incrementing in the set state, the execution of the second instruction comprising 3) obtaining a second TOD clock value; and 4) responsive to both the first instruction and the second instruction being STORE CLOCK instructions, storing the second TOD clock value in storage wherein the second TOD clock value obtained while the TOD clock is incrementing in the set state is always different than the first TOD clock value obtained while the TOD clock is incrementing in the set state; and 5) responsive to the second instruction being a STORE CLOCK FAST instruction, storing the second TOD clock value in storage wherein the obtained second time TOD clock value is identical to the obtained first TOD clock value.

In an embodiment, each of the first TOD clock value and the second TOD clock value comprise two fields consisting of an incrementing field and a non-incrementing field, wherein the incrementing field comprising a least significant bit, wherein the non-incrementing field comprises a most significant bit, wherein the incrementing field is incremented based on a system clock, wherein the non-incrementing field is not incrementing, wherein the most significant bit of the incrementing field is more significant than the high order bit of the non-incrementing field; wherein responsive to the second instruction being a STORE CLOCK instruction, the non-incrementing field comprising one or more non-zero value bits for ensuring that the second TOD clock value is unique; and responsive to the second instruction being a STORE CLOCK FAST instruction, the non-incrementing field consisting of all zero value bits.

In an embodiment, the quality of the TOD clock value stored by an instruction is indicated by the setting of a condition code value in a condition code comprising responsive to the TOD clock value being set, setting a condition code value of zero, and responsive to the TOD clock value being not set, setting a condition code value of one, wherein the TOD clock value indicates elapsed time since power to the clock was turned on; and responsive to the TOD clock being in either a stopped state or a not-operational state, setting a condition code value of three.

In an embodiment, the non-incrementing field consists of zero value bits when the TOD clock for the system is stopped.

In an embodiment, the STORE CLOCK FAST instruction is provided by the STORE CLOCK FAST facility that is indicated as being installed on a CPU of the system by an indicator bit readable by any one of a STORE FACILITY LIST instruction or a STORE FACILITY LIST EXTENDED instruction.

In an embodiment, a STORE CLOCK FAST machine instruction is obtained for execution, the STORE CLOCK FAST machine instruction being defined for computer execution according to a computer architecture, the STORE CLOCK FAST machine instruction comprising an opcode field, a field for identifying a base register (B2) and a displacement field (D2). The obtained STORE CLOCK FAST machine instruction is executed, the execution comprising:

arithmetically adding contents of the base register to the displacement field to determine a storage address; obtaining the TOD clock value; and storing the TOD clock value at the determined storage address.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block and schematic diagram illustrating a physical organization of an information processing system in accordance with an embodiment of the invention;

FIG. 2 is a block diagram illustrating a logical organization of an information processing system in accordance with an embodiment of the invention;

FIG. 3 shows the format of the STFLE instruction, its storage operand, and associated register usage;

FIG. 4 illustrates a method of recording a list of facilities by a guest program using the STFLE instruction;

FIG. 5 depicts an example instruction format for STCK and STCKF; and

FIG. 6 depicts an example TOD format of the invention.

DETAILED DESCRIPTION

FIG. 1 illustrates a computing environment which supports the performance of a method in accordance with an embodiment of the invention. In the computing environment illustrated in FIG. 1, a multi-processor system 100 includes a plurality of physical processors 101, also referred to as central processing units (“CPUs”), which are linked together via a common storage and interconnect subsystem 102, as shown in FIG. 1. The term physical processor denotes the hardware together with microcode, firmware and lowest level processing software for enabling the physical processor to support the operation of an operating system and processes subject to its control. While the multi-processor system 100 is illustrated with only three physical processors, it is possible for the multi-processor system to have fewer or a greater number of physical processors. The storage subsystem 102 contains certain storage resources which are subject to being shared among the physical processors.

FIG. 2 is a diagram illustrating a logical organization of an exemplary information processing system, which can be supported by the physical computing environment as illustrated and described above with reference to FIG. 1. Virtualization technology provides for the apportioning of the resources of a configuration to one or more logical configurations. The apportioning of the resources is under the control of a hypervisor program known as a “host program” (206). The resources, including one or more CPUs in the information processing system, memory, and I/O channels are apportioned to one or more logical configurations (known as guests). One means of such virtualization is for a host program known as the logical-partition (LPAR) manager to apportion the resources into guests called logical partitions (LPARs). These guests may include one or more versions of operating systems such as z/OS®, z/VM®, Linux®, etc., and the applications associated with those systems. Another means of such virtualization is for the host program to be a Virtual-Machine (VM) operating system which apportions its resources into guests called virtual machines. The virtual machine guests may include operating systems such as z/OS®, Linux®, and even another instance of the VM operating system.

The virtualization technology may be nested such that the VM operating system may run as a guest under the control of the LPAR hypervisor as the host program. In this case, the VM operating system is said to be operating at guest-level 1, and its guests operate at guest-level 2. FIG. 2 illustrates the apportioning of storage (200) to a host program (206) which can be the LPAR hypervisor or the VM operating system. Under the control of the host program are multiple guests (201, 202, 203, etc.). Each guest includes a system-control program, also known as an operating system (211, 212, 213) which controls the application programs (221, 222, and 223) running within the guest. The operating system (211) running in guest 1 (201) controls the application programs (221) within the guest. Similarly, the operating system (212) in guest 2 (202) controls its application programs (222), and the operating system (213) in guest 3 (203) controls its application programs (223).

As the host program, the hypervisor 206 allocates resources and keeps tracks of resources allocated to individual ones of the guests of the information processing system by entries made in tables and other data structures within host storage. Entries in tables, data structures, etc. in the operating system memory allow the host program to provide access to certain facilities of the information processing system in a way that is selective to particular guests. The term “facilities” refers to particular executable instructions, executable functions, and other particular ways of operating the information processing system. Facilities need not be granted universally to each guest. Since certain facilities can be specially geared to the needs of certain programs, through use of the methods and systems described herein, facilities can be selectively provided to only one or some of the guests, and not to other guests.

Among the limitations of the system described above as background to the invention is the requirement that the result of executing the STORE FACILIITY LIST (STFL) instruction be placed at a particular real address in memory. In addition to the execution result being not as easy to access when certain operating systems, e.g., Linux®, are used, this requirement of the prior art had the added consequence of limiting the amount and type of information obtained when executing the instruction to certain pre-defined information. These limitations are overcome by the method of recording a list of available facilities using the STORE FACILITY LIST EXTENDED (“STFLE”) instruction in accordance with an embodiment of the present invention. Through use of the new STFLE instruction, application programs are given control over the location for storing the execution result of the instruction, and are given more control over the amount of facilities information they can request.

FIG. 3 provides an illustration of the STORE FACILITY LIST EXTENDED instruction, showing the mnemonic (STFLE) and symbolic representation of its storage-operand specification, D₂(B₂), as would be coded by an assembly-language program; also shown is the instruction format [S] (601). The “S” instruction format indicates that STFLE has a two-byte operation code (opcode) and an operand that includes a 12-bit displacement field (D₂) added to an address contained in a base register (B₂). The machine format (602) of the STFLE instruction in memory shows the actual operation code (B2B0 hex) and the in-storage placement of the base register field and displacement field of the instruction. The storage operand of STFLE designates a logical address (that is, the address is virtual or real, depending on whether dynamic-address translation is enabled). When the STFLE instruction is executed, the CPU locates the storage operand based on the address provided by the instruction, and stores the facility indications at that address.

The length of the result field is implicitly specified by a count value contained in the rightmost bits (604) of general register 0 (“GR0”, 603). Bits 56-63 of general register 0 contain a value representing one less than the number of doublewords provided in the result field. For example, a value of 2 indicates that the result field can accommodate three doublewords (24 bytes) of data. The eight bit count value allows a result of up to 256 doublewords to be returned when executing the instruction.

If the length field (604) in general register 0 (603) specifies sufficient doublewords to hold the result, the entire facility list is stored and the instruction ends by setting condition code 0. If the length field in general register 0 does not specify sufficient doublewords to hold the entire result, the number of doublewords specified are stored, and the instruction ends by setting condition code 3. In either case, general register 0 is updated to contain one less than the number of doublewords required to contain all of the facility bits that are assigned for the model.

When the STFLE instruction is executed by the highest-level host program (that is, a program for which there is no hypervisor), the instruction operates as described above. When the STFLE instruction is executed by a guest program, the CPU interprets the instruction by using information provided by the host program, as described below.

FIG. 4 shows the execution of the STFLE instruction in a guest environment. During the initialization of a host program, the STFLE instruction is executed to determine the facilities available to the host configuration. The host program may choose to alter the facility list that is made available to its guests. This can occur when a facility provided by the CPU requires assistance of the host program to operate correctly, and the host program is unable to provide that assistance. This can be the case when a back-level VM system runs on a newer CPU, for example. Another case where the host program may choose to alter the facility list available to a guest is when the guest simulates a facility which is not provided on the CPU.

In order to dispatch a guest configuration, the host program establishes certain guest parameters in a state description (702) in host storage (701) and executes a START INTERPRETIVE EXECUTION instruction. Within the state description is a pointer to a facility-list designation (703) that points to the facility list (704) to be provided to the guest associated with the state description. The host program constructs the facility list to contain facility bits that the host program discovers by its own execution of STFLE, while removing facility bits for any facilities that the host program cannot support. In addition, the host program adds facility bits to the facility list for facilities which are not physically installed in the information processing system, but which, nevertheless, the host program emulates for the guest.

When a guest (a system control program (e.g., 211, FIG. 2) or application program (e.g., Application Program 1 (221), FIG. 2)) issues a STFLE instruction (711), it designates the address of one or more doublewords (712) in guest storage (710) in which the result is to be placed. The CPU's execution of the STFLE instruction for a guest causes the host-specified facility bits for the guest (704) to be copied (720) into the guest's storage location (712). This copying is performed by the CPU without any intervention by the host program. If the guest has not provided sufficient doublewords, then only the number of doublewords specified by the guest is copied, and the condition code indicates an incomplete result.

If the facility-list designation (703) in the state description (702) contains all zeros and the guest executes a STFLE instruction, an instruction interception occurs, and control returns to the host program. If the facility-list designation (703) designates an unavailable storage location, then a validity interception is recognized, and control returns to the host program.

The present invention is not limited to any particular CPU architecture, however in order to provide a clear description of a preferred embodiment, the invention will be described herein as implemented according to the IBM® z/Architecture®.

Each CPU in an installation provides access to a time-of-day (TOD) clock, which is shared by all CPUs in the installation.

The timing facilities include three facilities for measuring time: the TOD clock, the clock comparator, and the CPU timer. A TOD programmable register is associated with the TOD clock. In a multiprocessing configuration, a single TOD clock is shared by all CPUs. Each CPU has its own clock comparator, CPU timer, and TOD programmable register.

Decision Making

Facilities for decision making are provided by the BRANCH ON CONDITION, BRANCH RELATIVE ON CONDITION, and BRANCH RELATIVE ON CONDITION LONG instructions. These instructions inspect a condition code that reflects the result of a majority of the arithmetic, logical, and I/O operations. The condition code, which consists of two bits, provides for four possible condition-code settings: 0, 1, 2, and 3. The specific meaning of any setting depends on the operation that sets the condition code. For example, the condition code reflects such conditions as zero, nonzero, first operand high, equal, overflow, and sub-channel busy. Once set, the condition code remains unchanged until modified by an instruction that causes a different condition code to be set.

CPU

The central processing unit (CPU) is the controlling center of the system. It contains the sequencing and processing facilities for instruction execution, interruption action, timing functions, initial program loading, and other machine-related functions. The physical implementation of the CPU may differ among models, but the logical function remains the same. The result of executing an instruction is the same for each model, providing that the program complies with the compatibility rules.

The CPU, in executing instructions, can process binary integers and floating-point numbers (binary and hexadecimal) of fixed length, decimal integers of variable length, and logical information of either fixed or variable length. Processing may be in parallel or in series; the width of the processing elements, the multiplicity of the shifting paths, and the degree of simultaneity in performing the different types of arithmetic differ from one model of CPU to another without affecting the logical results. Instructions which the CPU executes fall into seven classes: general, decimal, floating-point-support (FPS), binary-floating-point (BFP), hexadecimal floating-point (HFP), control, and I/O instructions. The general instructions are used in performing binary-integer-arithmetic operations and logical, branching, and other non-arithmetic operations. The decimal instructions operate on data in the decimal format. The BFP and HFP instructions operate on data in the BFP and HFP formats, respectively, while the FPS instructions operate on floating-point data independent of the format or convert it from one format to the other. The privileged control instructions and the I/O instructions can be executed only when the CPU is in the supervisor state; the semi-privileged control instructions can be executed in the problem state, subject to the appropriate authorization mechanisms.

The CPU provides registers which are available to programs but do not have addressable representations in main storage. They include the current program-status word (PSW), the general registers, the floating-point registers and floating-point-control register, the control registers, the access registers, the prefix register, and the registers for the clock comparator and the CPU timer. Each CPU in an installation provides access to a time-of-day (TOD) clock, which is shared by all CPUs in the installation. The instruction operation code determines which type of register is to be used in an operation.

Time-of-Day Clock

The time-of-day (TOD) clock provides a high-resolution measure of real time suitable for the indication of date and time of day. The cycle of the clock is approximately 143 years. A single TOD clock is shared by all CPUs in the configuration.

Format

The TOD clock is a 104-bit register. It is a binary counter with the format shown FIG. 6.

The TOD clock nominally is incremented by adding a one in bit position 51 every microsecond. In models having a higher or lower resolution, a different bit position is incremented at such a frequency that the rate of advancing the clock is the same as if a one were added in bit position 51 every microsecond. The resolution of the TOD clock is such that the incrementing rate is comparable to the instruction execution rate of the model.

When incrementing of the clock causes a carry to be propagated out of bit position 0, the carry is ignored, and counting continues from zero. The program is not alerted, and no interruption condition is generated as a result of the overflow.

The operation of the clock is not affected by any normal activity or event in the system. Incrementing of the clock does not depend on whether the wait-state bit of the PSW is one or whether the CPU is in the operating, load, stopped, or check-stop state. Its operation is not affected by CPU, initial-CPU, or clear resets or by initial program loading. Operation of the clock is also not affected by the setting of the rate control or by an initial-machine-loading operation. Depending on the model and the configuration, the TOD clock may or may not be powered independent of the CPU.

States

The following states are distinguished for the TOD clock: Set, not set, stopped, error, and not operational. The state determines the condition code set by execution of STORE CLOCK, STORE CLOCK EXTENDED, and STORE CLOCK FAST. The clock is incremented, and is said to be running, when it is in either the set state or the not-set state.

Not-Set State: When the power for the clock is turned on, the clock is set to zero, and the clock enters the not-set state. The clock is incremented when in the not-set state. When the TOD-clock-steering facility is installed, the TOD clock is never reported to be in the not-set state, as the TOD clock is placed in the set state as part of the initial-machine-loading (IML) process. When the clock is in the not-set state, execution of STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST causes condition code 1 to be set and the current value of the running clock to be stored.

Stopped State The clock enters the stopped state when SET CLOCK is executed and the execution results in the clock being set. This occurs when SET CLOCK is executed without encountering any exceptions and either any manual TOD-clock control in the configuration is set to the enable-set position or the TOD-clock-control-override control, bit 42 of control register 14, is one. The clock can be placed in the stopped state from the set, not-set, and error states. The clock is not incremented while in the stopped state.

When the clock is in the stopped state, execution of STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST causes condition code 3 to be set and the value of the stopped clock to be stored.

Set State The clock enters the set state only from the stopped state. The change of state is under control of the TOD-clock-sync-control bit, bit 34 of control register 0, of the CPU which most recently caused the clock to enter the stopped state. If the bit is zero, 0 51 64 103 1 microsecond Chapter 4. Control 4-37 the clock enters the set state at the completion of execution of SET CLOCK. If the bit is one, the clock remains in the stopped state until the bit is set to zero on that CPU or until another CPU executes a SET CLOCK instruction affecting the clock. If an external time reference (ETR) is installed, a signal from the ETR may be used to set the set state from the stopped state.

Programming Note: The STP facility does not provide a signal that will cause the clock to transition from the stopped state to the set state. If SET CLOCK is executed when the configuration is in STP-timing mode and bit 34 {2} of control register 0 is one, the clock remains in the stopped state until the bit is set to zero on that CPU or until another CPU executes a SET CLOCK instruction affecting the clock. Incrementing of the clock begins with the first stepping pulse after the clock enters the set state.

In the absence of an ETR, depending on the model, the clock may enter the set state from the stopped state without any programming action.

When the clock is in the set state, execution of STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST causes condition code 0 to be set and the current value of the running clock to be stored.

Error State The clock enters the error state when a malfunction is detected that is likely to have affected the validity of the clock value. It depends on the model whether the clock can be placed in this state. A timing-facility-damage machine-check-interruption condition is generated on each CPU in the configuration whenever the clock enters the error state. When the TOD-clock-steering facility is installed, the TOD clock is never reported to be in the error state. Errors in the TOD clock cause a system check stop.

When STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST is executed and the clock is in the error state, condition code 2 is set, and the value stored is zero.

Not-Operational State: The clock is in the not-operational state when its power is off or when it is disabled for maintenance. It depends on the model whether the clock can be placed in this state. Whenever the clock enters the not-operational state, a timing-facility-damage machine-check-interruption condition is generated on each CPU in the configuration. When the TOD-clock-steering facility is installed, the TOD clock is never reported to be in the not-operational state.

When the clock is in the not-operational state, execution of STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST causes condition code 3 to be set, and zero is stored.

Programming Note: When the TOD-clock-steering facility is installed, the TOD clock has only two states, the set state and the stopped state. Assuming proper operation by the operating system, problem programs are never dispatched while the TOD clock is in the stopped state. Thus, as observed by the problem program, the TOD clock is always in the set state and there is no need to test the condition code after issuing STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST.

Changes in Clock State

When the TOD-clock-steering facility is not installed, and the TOD clock changes value because of the execution of SET CLOCK or changes state, interruption conditions pending for the clock comparator and CPU timer may or may not be recognized for up to 1.048576 seconds (220 microseconds) after the change.

When the TOD-clock-steering facility is installed and SET CLOCK is issued, interruption conditions for the clock comparator and CPU timer may or may not be recognized while the physical clock is in the stopped state. After the physical clock enters the set state, interruption conditions for the clock comparator are not necessarily recognized until one of the following instructions is issued: SET CLOCK COMPARATOR (SCKC), STORE CLOCK (STCK), or STORE CLOCK EXTENDED (STCKE). After the physical clock enters the set state, interruption conditions for the CPU timer are not necessarily recognized until SET CPU TIMER (SPT) is issued. If a CPU is in the wait state when the physical clock is set or changes state, the CPU does not necessarily recognize interruption conditions for the clock comparator or CPU timer until after it leaves the wait state and the appropriate aforementioned instruction is executed.

When the TOD-clock-steering facility is installed and the logical TOD clock is changed by PTFF-ATO or PTFF-STO, interruption conditions for the clock comparator are not necessarily recognized until one of the following instructions is issued: SET CLOCK COMPARATOR (SCKC), STORE CLOCK (STCK), or STORE CLOCK EXTENDED (STCKE). If a CPU is in the wait state when the logical TOD clock is changed, the CPU may or may not recognize interruption conditions for the clock comparator until after it leaves the wait state and one of the aforementioned instructions is executed. The CPU timer and CPU-timer interruptions are not affected by PTFF-STO and PTFF-ATO.

The results of channel-subsystem-monitoring-facility operations may be unpredictable as a result of changes to the TOD clock.

Setting and Inspecting the Clock

The clock can be set to a specified value by execution of SET CLOCK if the manual TOD-clock control of any CPU in the configuration is in the enable-set position or the TOD-clock-control-override control, bit 42 of control register 14, is one. SET CLOCK sets bits of the clock with the contents of corresponding bit positions of a doubleword operand in storage.

Setting the clock replaces the values in all bit positions from bit position 0 through the rightmost position that is incremented when the clock is running. However, on some models, the rightmost bits starting at or to the right of bit 52 of the specified value are ignored, and zeros are placed in the corresponding positions of the clock. Zeros are also placed in positions to the right of bit position 63 of the clock.

The TOD clock can be inspected by executing STORE CLOCK or STORE CLOCK FAST, which causes bits 0-63 of the clock to be stored in an eightbyte operand in storage, or by executing STORE CLOCK EXTENDED, which causes bits 0-103 of the clock to be stored in bytes 1-13 of a 16-byte operand in storage. STORE CLOCK EXTENDED stores zeros in the leftmost byte, byte 0, of its storage operand, and it obtains the TOD programmable field from bit positions 16-31 of the TOD programmable register and stores it in byte positions 14 and 15 of the storage operand.

Two executions of STORE CLOCK or STORE CLOCK EXTENDED, possibly on different CPUs in the same configuration, always store different values of the clock if the clock is running.

The values stored for a running clock by STORE CLOCK or STORE CLOCK EXTENDED always correctly imply the sequence of execution of these instructions by one or more CPUs for all cases where the sequence can be discovered by the program. To ensure that unique values are obtained when the value of a running clock is stored, nonzero values may be stored in positions to the right of the rightmost incremented bit position. When the value of a running clock is stored by STORE CLOCK EXTENDED, the value in bit positions 64-103 of the clock (bit positions 72-111 of the storage operand) is always nonzero; this ensures that values stored by STORE CLOCK EXTENDED are always unique when compared with values stored by STORE CLOCK or STORE CLOCK FAST, extended on the right with zeros.

For the purpose of establishing uniqueness and sequence of occurrence of the results of STORE CLOCK and STORE CLOCK EXTENDED, the 64-bit value provided by STORE CLOCK may be considered to be extended to 104 bits by appending 40 zeros on the right, with the STORE CLOCK value and STORE CLOCK EXTENDED bits 8-111 then both being treated as 104-bit unsigned binary integers.

Two executions of STORE CLOCK FAST, or an execution of STORE CLOCK FAST and STORE CLOCK, either on the same or different CPUs, do not necessarily return different values of the clock if the clock is running. Thus, the values returned by STORE CLOCK FAST do not necessarily indicate the correct sequence of execution of the instruction by one or more CPUs.

Provided the TOD clock is in the not-set or set state and does not change state, and, in the absence of a carry out of bit position 0 of the TOD clock, then the value of bits 0-63 of the TOD clock as stored by STORE CLOCK FAST are never less than the value of bits 0-63 of the TOD clock as stored by a previous STORE CLOCK EXTENDED and never more than the value of bits 0-63 of the TOD clock as stored by a subsequent STORE CLOCK EXTENDED. In a configuration where more than one CPU accesses the clock, SET CLOCK is interlocked such that the entire contents appear to be updated concurrently; that is, if SET CLOCK instructions are executed simultaneously by two CPUs, the final result is either one or the other value. If SET CLOCK is executed by one CPU and STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST by the other, the result obtained by STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST is either the entire old value or the entire new value. When SET CLOCK is executed by one CPU, a STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST instruction executed by another CPU may find the clock in the stopped state even when the TOD-clock-sync-control bit, bit 34 of control register 0, of each CPU is zero. Since the clock enters the set state before incrementing, the first STORE CLOCK, STORE CLOCK EXTENDED, or STORE CLOCK FAST instruction executed after the clock enters the set state may still find the original value introduced by SET CLOCK.

TOD Programmable Register

Each CPU has a TOD programmable register. Bits 16-31 of the register contain the programmable field that is appended on the right to the TOD-clock value by STORE CLOCK EXTENDED.

The register is loaded by SET CLOCK PROGRAMMABLE FIELD. The contents of the register are reset to a value of all zeros by initial CPU reset.

The guest TOD-clock programmable field is obtained from bytes 110 and 111 of the state description on entry to the interpretive-execution mode. The host TOD-clock programmable field is preserved on entry to the interpretive-execution mode and is restored on exit.

The TOD programmable field is retainable.

The TOD programmable field is not included in the timing subset facility.

Programming Notes:

1. Bit position 31 of the clock is incremented every 1.048576 seconds; for some applications, reference to the leftmost 32 bits of the clock may provide sufficient resolution.

2. Communication between systems is facilitated by establishing a standard time origin that is the calendar date and time to which a clock value of zero corresponds. Jan. 1, 1900, 0 a.m. Coordinated Universal Time (UTC) is recommended as this origin, and it is said to begin the standard epoch for the clock. This is also the epoch used when the TOD clock is synchronized to the external time reference (ETR), and, for this reason, the epoch is sometimes referred to as ETR time. The former term, Greenwich Mean Time (GMT), is now obsolete and has been replaced with the more precise UTC.

3. Historically, one of the most important uses of standard time has been for navigation. Prior to 1972, standard time, then called GMT, was defined to have a variable-length second and was synchronized to within 100 milliseconds of the rotational position of the earth. Synchronization was accomplished by occasional changes in the length of the second, typically in parts per billion, and also by occasional insertion and deletion of small increments of time, typically 50 or 100 milliseconds. Beginning in 1972, a new standard time scale, called UTC, was defined to have a fixed-length second and be kept synchronized to within 900 milliseconds of the rotational position of the earth by means of occasional adjustments of exactly one second called a leap second. The change from GMT to UTC occurred between the last second of the day on Dec. 31, 1971 and the first second of the day on Jan. 1, 1972 and included insertion of 107.758 milliseconds in the standard time scale to make UTC exactly 10 seconds behind International Atomic Time (TAI). For reasons of simplicity in this document, the term UTC is sometimes extrapolated backward before 1972 by assuming no time adjustments in that time scale before 1972. For the same reasons, conversion between ETR time and UTC does not take into consideration the time adjustments prior to 1972, and, thus, ETR time differs from TAI by a fixed amount of 10 seconds. Because of the occurrence of 23 leap seconds, UTC now is behind TAI by 33 seconds.

4. A program using the clock value as a time-of-day and calendar indication must be consistent with the programming support under which the program is to be executed. If the programming support uses the standard epoch, bit 0 of the clock remains one through the years 1972-2041. (Bit 0 turned on at 11:56:53.685248 (UTC) May 11, 1971.) Ordinarily, testing bit 0 for a one is sufficient to determine if the clock value is in the standard epoch.

5. In converting to or from the current date or time, the programming support must take into account that “leap seconds” have been inserted or deleted because of time-correction standards. When the TOD clock has been set correctly to a time within the standard epoch, the sum of the accumulated leap seconds must be subtracted from the clock time to determine UTC time.

6. Because of the limited accuracy of manually setting the clock value, the rightmost bit positions of the clock, expressing fractions of a second, are normally not valid as indications of the time of day. However, they permit elapsed-time measurements of high resolution.

7. -

8. --

9. The stepping value of TOD-clock bit position 63, if implemented, is 2-12 microseconds, or approximately 244 picoseconds. This value is called a clock unit.

10. --

11. In a multiprocessing configuration, after the TOD clock is set and begins running, the program should delay activity for 220 microseconds (1.048576 seconds) to ensure that the CPU timer and clock-comparator interruption conditions are recognized by the CPU.

12. Due to the sequencing rules for the results of STORE CLOCK and STORE CLOCK EXTENDED, the execution of STORE CLOCK may be considerably slower than that of STORE CLOCK EXTENDED and STORE CLOCK FAST.

13. Uniqueness of TOD-clock values can be extended to apply to processors in separate configurations by including a configuration identification in the TOD programmable field.

14. At some time in the future, new models will use a carry from bit position 0 of the TOD clock to increment an additional eight-bit binary counter. STORE CLOCK EXTENDED will store the contents of this counter in byte position 0 of its storage operand. A variation of SET CLOCK will set the counter, as well as the TOD clock. Variations of SET CLOCK COMPARATOR and STORE CLOCK COMPARATOR will manipulate a comparable byte at the left of the clock comparator. These actions will allow the TOD clock to continue to measure time within the standard epoch after the current 143-year limit caused by a carry from bit position 0 has been exceeded, and they will allow continued use of the clock comparator. It may be desired to have programs that process 16-byte STORE CLOCK EXTENDED operands take these future developments into account.

TOD-Clock Synchronization

The following functions are provided if the configuration is part of an ETR network:

-   -   A clock in the stopped state, with the TOD-clocksync-control bit         (bit 34 of control register 0) set to one, is placed in the set         state and starts incrementing when an ETR signal occurs.     -   The stepping rates for the TOD clock and the ETR are         synchronized.     -   Bits 32 through the rightmost incremented bit of a clock in the         set state are compared with the same bits of the ETR. An unequal         condition is signaled by an external-damage machine-check         interruption condition. The machine-check-interruption condition         may not be recognized for up to 1.048576 seconds (220         microseconds) after the unequal condition occurs.

When the server timer protocol (STP) facility is installed, the timing mode, timing state and STPclock-source state are defined as described below.

Timing Mode

The timing mode specifies the method by which the TOD clock is maintained for purposes of synchronization within a timing network. A TOD clock operates in one of the following timing modes:

Local Timing Mode: When the configuration is in local timing mode, the TOD clock has been initialized to a local time and is being stepped at the rate of the local hardware oscillator. The configuration is not part of a synchronized timing network.

ETR Timing Mode: When the configuration is in ETR-timing mode, the TOD clock has been initialized to the ETR and is being stepped by stepping signals from ETR. To be in ETR-timing mode, the configuration must be part of an ETR network.

STP Timing Mode: When the configuration is in STP-timing mode, the TOD clock has been initialized to coordinated server time (CST) and is being stepped at the rate of the local hardware oscillator. In STP timing mode, the TOD clock is steered so as to maintain, or attain, synchronization with CST. To be in STP-timing mode, the configuration must be part of an STP network.

Timing State

The timing state indicates the synchronization state of the TOD clock with respect to the timing network reference time. Synchronized State: When a configuration is in the synchronized timing state, the TOD clock is in synchronization with the timing-network reference time as defined below:

-   -   If the configuration is in ETR-timing mode, the configuration is         synchronized with the ETR.     -   If the configuration is in STP timing mode, the configuration is         synchronized with coordinated server time (CST).

A configuration that is in the local-timing or uninitialized-timing mode is never in the synchronized state.

Unsynchronized State: When a configuration is in the unsynchronized timing state, the TOD clock is not in synchronization with the timing network reference time as defined below:

-   -   If the configuration is in ETR-timing mode, the configuration         has lost synchronization with the ETR.     -   If the configuration is in STP timing mode, the configuration         has lost or has not been able to attain synchronization with         coordinated server time (CST). The configuration is out of         synchronization with CST when the TOD clock differs from CST by         an amount that exceeds a model dependent         STP-sync-check-threshold value.

Stopped State: When a configuration is in the stopped state, the TOD clock is either in the stopped state or TOD-clock recovery is in progress. After TOD-clock recovery completes, the TOD clock enters either the synchronized or unsynchronized state.

STP Clock Source State

The STP-clock-source state indicates whether a usable STP-clock source is available. The STP-clock source is used to determine the coordinated server time (CST) required to be able to synchronize the TOD clock.

Not Usable: The not-usable-STP-clock-source state indicates that a usable STP-clock source is not available to the STP facility. When a usable STP-clock source is not available, CST can not be determined.

Usable: The usable-STP-clock-source state indicates that a usable STP-clock source is available to the STP facility. When a usable STP-clock source is available, CST has been determined and can be used to synchronize the TOD clock to the STP network.

Programming Notes:

1. ETR TOD-clock synchronization provides for synchronizing and checking only bits 32 through the rightmost incremented bit of the TOD clock. Bits 0-31 of the TOD clock may be different from those of the ETR.

2. If the configuration is part of an ETR network, SET CLOCK must place all zeros in bit positions 32 through the rightmost incremented bit position of the TOD clock; otherwise, an external-damage machine-check-interruption condition will be recognized.

Facilities installed in a configuration are indicated by facility bits stored by the STORE FACILITY LIST (STFL) and STORE FACILITY LIST EXTENDED (STFLE) instructions. STORE FACILITY LIST stores an indication of up to 32 facilities in the word at real location 200. STORE FACILITY LIST EXTENDED stores a variable number of doublewords containing facility bits in a program-specified location.

The following table shows the meanings of some of the assigned facility bits. (Bit 25 indicates whether the store-clock-fast facility is installed)

Bit Meaning when Bit is One

-   -   21 The extended-immediate facility is installed in the         z/Architecture architectural mode.     -   22 The extended-translation facility 3 is installed in the         z/Architecture architectural mode.     -   23 The HFP-unnormalized-extension facility is installed in the         z/Architecture architectural mode.     -   24 The ETF2-enhancement facility is installed.     -   25 The store-clock-fast facility is installed in the         z/Architecture architectural mode.     -   26 The TOD-clock-steering facility is installed in the         z/Architecture architectural mode.     -   27 The ETF3-enhancement facility is installed in the         z/Architecture architectural mode.

STORE CLOCK (STCK) and STORE CLOCK FAST (STCKF):

Referring to FIG. 5, the current value of bits 0-63 of the TOD clock is stored in the eight-byte field designated by the second operand address, provided the clock is in the set, stopped, or not-set state. When the clock is stopped, zeros are stored in positions to the right of the rightmost bit position that is incremented when the clock is running. For STORE CLOCK, when the value of a running clock is stored, nonzero values may be stored in positions to the right of the rightmost incremented bit; this is to ensure that a unique value is stored. For STORE CLOCK FAST, when the value of a running clock is stored, bits to the right of the rightmost bit that is incremented are stored as zeros. Zeros are stored at the operand location when the clock is in the error state or the not-Operational state. The quality of the clock value stored by the instruction is indicated by the resultant condition-code setting. For STORE CLOCK, a serialization function is performed before the value of the clock is fetched and again after the value is placed in storage.

Resulting Condition Code:

0 Clock in set state

1 Clock in not-set state

2 Clock in error state

3 Clock in stopped state or not-operational state

Program Exceptions:

-   -   Access (store, operand 2)     -   Operation (STCKF, if the store-clock-fast facility is not         installed)

Programming Notes:

Bit position 31 of the clock is incremented every 1.048576 seconds; hence, for timing applications involving human responses, the leftmost clock word may provide sufficient resolution.

Condition code 0 normally indicates that the clock has been set by the control program. Accordingly, the value may be used in elapsed time measurements and as a valid time-of-day and calendar indication. Condition code 1 indicates that the clock value is the elapsed time since the power for the clock was turned on. In this case, the value may be used in elapsed-time measurements but is not a valid time-of-day indication. Condition codes 2 and 3 mean that the value provided by STORE CLOCK cannot be used for time measurement or indication.

Condition code 3 indicates that the clock is in either the stopped state or the not-operational state. These two states can normally be distinguished because an all-zero value is stored when the clock is in the not-operational state.

If a problem program written for z/Architecture® is to be executed also on a system in the System/370 mode, then the program should take into account that, in the System/370 mode, the value stored when the condition code is 2 is not necessarily zero.

Two executions of STORE CLOCK FAST, or an execution of STORE CLOCK FAST and STORE CLOCK, either on the same or different CPUs, do not necessarily return different values of the clock if the clock is running. Thus, the values returned by STORE CLOCK FAST do not necessarily indicate the correct sequence of execution of the instruction by one or more CPUs. 6. When the TOD-clock-steering facility is installed, and assuming a valid operating system, then, for the problem program, the TOD clock is always in the set state and there is no need to test the condition code after issuing STORE CLOCK or STORE CLOCK FAST.

The methods described herein are typically performed by hardware, e.g., a CPU, or by a combination of hardware and one or more programs, e.g., microcode, millicode, firmware, software and the like, executed by the hardware. Such program can be recorded on a recording medium, e.g., storage including electronic, magnetic, optical or other technology. The recording medium can be embodied within the information processing system or may be package for distribution or delivery, via a portable medium such as a disk, or via electronic delivery means, e.g., over a network.

While the invention has been described in accordance with certain preferred embodiments thereof, many modifications and enhancements can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below. 

1. A computer implemented method for executing instructions for storing a value of a time-of-day (TOD) clock, the method comprising: obtaining a first instruction for execution by a Central Processing Unit (CPU) of one or more CPUs in the system; and initiating execution of the obtained first instruction while the TOD clock is incrementing in a set state, the execution of the first instruction comprising 1) and 2): 1) obtaining a first TOD clock value; and 2) storing the first TOD clock value in storage; obtaining a second instruction for execution by a CPU of the one or more CPUs in the system; and subsequent to the initiating execution of the first instruction, initiating execution of the obtained second instruction while the TOD clock is incrementing in the set state, the execution of the second instruction comprising 3) through 5); 3) obtaining a second TOD clock value; and 4) responsive to both the first instruction and the second instruction being STORE CLOCK instructions, storing the second TOD clock value in storage wherein the second TOD clock value obtained while the TOD clock is incrementing in the set state is always different than the first TOD clock value obtained while the TOD clock is incrementing in the set state; and 5) responsive to the second instruction being a STORE CLOCK FAST instruction, storing the second TOD clock value in storage wherein the obtained second time TOD clock value is identical to the obtained first TOD clock value.
 2. The method according to claim 1, wherein each of the first TOD clock value and the second TOD clock value comprise two fields consisting of an incrementing field and a non-incrementing field, wherein the incrementing field comprising a least significant bit, wherein the non-incrementing field comprises a most significant bit, wherein the incrementing field is incremented based on a system clock, wherein the non-incrementing field is not incrementing, wherein the most significant bit of the incrementing field is more significant than the high order bit of the non-incrementing field further comprising: responsive to the second instruction being a STORE CLOCK instruction, the non-incrementing field comprising one or more non-zero value bits for ensuring that the second TOD clock value is unique; and responsive to the second instruction being a STORE CLOCK FAST instruction, the non-incrementing field consisting of all zero value bits.
 3. The method according to claim 2, wherein the quality of the TOD clock value stored by an instruction is indicated by the setting of a condition code value in a condition code comprising: responsive to the TOD clock value being set, setting a condition code value of zero; responsive to the TOD clock value being not set, setting a condition code value of one, wherein the TOD clock value indicates elapsed time since power to the clock was turned on; and responsive to the TOD clock being in either a stopped state or a not-operational state, setting a condition code value of three.
 4. The method according to claim 3, wherein the non-incrementing field consists of zero value bits when the TOD clock for the system is stopped.
 5. The method according to claim 1, wherein the STORE CLOCK FAST instruction is provided by the STORE CLOCK FAST facility that is indicated as being installed on a CPU of the system by an indicator bit readable by any one of a STORE FACILITY LIST instruction or a STORE FACILITY LIST EXTENDED instruction.
 6. The method according to claim 1, further comprising: obtaining for execution a STORE CLOCK FAST machine instruction, the STORE CLOCK FAST machine instruction being defined for computer execution according to a computer architecture, the STORE CLOCK FAST machine instruction comprising an opcode field, a field for identifying a base register (B2) and a displacement field (D2); executing the obtained STORE CLOCK FAST machine instruction, the execution comprising: 1) arithmetically adding contents of the base register to the displacement field to determine a storage address; 2) obtaining the TOD clock value; and 3) storing the TOD clock value at the determined storage address.
 7. A computer program product for executing instructions for storing a value of a time-of-day (TOD) clock, the computer program product comprising: obtaining a first instruction for execution by a Central Processing Unit (CPU) of one or more CPUs in the system; and initiating execution of the obtained first instruction while the TOD clock is incrementing in a set state, the execution of the first instruction comprising 1) and 2): 1) obtaining a first TOD clock value; and 2) storing the first TOD clock value in storage; obtaining a second instruction for execution by a CPU of the one or more CPUs in the system; and subsequent to the initiating execution of the first instruction, initiating execution of the obtained second instruction while the TOD clock is incrementing in the set state, the execution of the second instruction comprising 3) through 5); 3) obtaining a second TOD clock value; and 4) responsive to both the first instruction and the second instruction being STORE CLOCK instructions, storing the second TOD clock value in storage wherein the second TOD clock value obtained while the TOD clock is incrementing in the set state is always different than the first TOD clock value obtained while the TOD clock is incrementing in the set state; and 5) responsive to the second instruction being a STORE CLOCK FAST instruction, storing the second TOD clock value in storage wherein the obtained second time TOD clock value is identical to the obtained first TOD clock value.
 8. The computer program product according to claim 7, wherein each of the first TOD clock value and the second TOD clock value comprise two fields consisting of an incrementing field and a non-incrementing field, wherein the incrementing field comprising a least significant bit, wherein the non-incrementing field comprises a most significant bit, wherein the incrementing field is incremented based on a system clock, wherein the non-incrementing field is not incrementing, wherein the most significant bit of the incrementing field is more significant than the high order bit of the non-incrementing field further comprising: responsive to the second instruction being a STORE CLOCK instruction, the non-incrementing field comprising one or more non-zero value bits for ensuring that the second TOD clock value is unique; and responsive to the second instruction being a STORE CLOCK FAST instruction, the non-incrementing field consisting of all zero value bits.
 9. The computer program product according to claim 8, wherein the quality of the TOD clock value stored by an instruction is indicated by the setting of a condition code value in a condition code comprising: responsive to the TOD clock value being set, setting a condition code value of zero; responsive to the TOD clock value being not set, setting a condition code value of one, wherein the TOD clock value indicates elapsed time since power to the clock was turned on; and responsive to the TOD clock being in either a stopped state or a not-operational state, setting a condition code value of three.
 10. The computer program product according to claim 9, wherein the non-incrementing field consists of zero value bits when the TOD clock for the system is stopped.
 11. The computer program product according to claim 7, wherein the STORE CLOCK FAST instruction is provided by the STORE CLOCK FAST facility that is indicated as being installed on a CPU of the system by an indicator bit readable by any one of a STORE FACILITY LIST instruction or a STORE FACILITY LIST EXTENDED instruction.
 12. The computer program product according to claim 1, further comprising: obtaining for execution a STORE CLOCK FAST machine instruction, the STORE CLOCK FAST machine instruction being defined for computer execution according to a computer architecture, the STORE CLOCK FAST machine instruction comprising an opcode field, a field for identifying a base register (B2) and a displacement field (D2); executing the obtained STORE CLOCK FAST machine instruction, the execution comprising: 1) arithmetically adding contents of the base register to the displacement field to determine a storage address; 2) obtaining the TOD clock value; and 3) storing the TOD clock value at the determined storage address.
 13. A system for executing instructions for storing a value of a time-of-day (TOD) clock, the system comprising: a storage for holding instructions and data; one or more Central Processing Units for accessing the storage; a TOD clock; and a system clock for incrementing the TOD clock, the system capable of performing a method comprising: obtaining a first instruction for execution by a Central Processing Unit (CPU) of one or more CPUs in the system; and initiating execution of the obtained first instruction while the TOD clock is incrementing in a set state, the execution of the first instruction comprising 1) and 2): 1) obtaining a first TOD clock value; and 2) storing the first TOD clock value in storage; obtaining a second instruction for execution by a CPU of the one or more CPUs in the system; and subsequent to the initiating execution of the first instruction, initiating execution of the obtained second instruction while the TOD clock is incrementing in the set state, the execution of the second instruction comprising 3) through 5); 3) obtaining a second TOD clock value; and 4) responsive to both the first instruction and the second instruction being STORE CLOCK instructions, storing the second TOD clock value in storage wherein the second TOD clock value obtained while the TOD clock is incrementing in the set state is always different than the first TOD clock value obtained while the TOD clock is incrementing in the set state; and 5) responsive to the second instruction being a STORE CLOCK FAST instruction, storing the second TOD clock value in storage wherein the obtained second time TOD clock value is identical to the obtained first TOD clock value.
 14. The system according to claim 13, wherein each of the first TOD clock value and the second TOD clock value comprise two fields consisting of an incrementing field and a non-incrementing field, wherein the incrementing field comprising a least significant bit, wherein the non-incrementing field comprises a most significant bit, wherein the incrementing field is incremented based on a system clock, wherein the non-incrementing field is not incrementing, wherein the most significant bit of the incrementing field is more significant than the high order bit of the non-incrementing field further comprising: responsive to the second instruction being a STORE CLOCK instruction, the non-incrementing field comprising one or more non-zero value bits for ensuring that the second TOD clock value is unique; and responsive to the second instruction being a STORE CLOCK FAST instruction, the non-incrementing field consisting of all zero value bits.
 15. The system according to claim 14, wherein the quality of the TOD clock value stored by an instruction is indicated by the setting of a condition code value in a condition code comprising: responsive to the TOD clock value being set, setting a condition code value of zero; responsive to the TOD clock value being not set, setting a condition code value of one, wherein the TOD clock value indicates elapsed time since power to the clock was turned on; and responsive to the TOD clock being in either a stopped state or a not-operational state, setting a condition code value of three.
 16. The system according to claim 15, wherein the non-incrementing field consists of zero value bits when the TOD clock for the system is stopped.
 17. The system according to claim 13, wherein the STORE CLOCK FAST instruction is provided by the STORE CLOCK FAST facility that is indicated as being installed on a CPU of the system by an indicator bit readable by any one of a STORE FACILITY LIST instruction or a STORE FACILITY LIST EXTENDED instruction.
 18. The system according to claim 13, further comprising: obtaining for execution a STORE CLOCK FAST machine instruction, the STORE CLOCK FAST machine instruction being defined for computer execution according to a computer architecture, the STORE CLOCK FAST machine instruction comprising an opcode field, a field for identifying a base register (B2) and a displacement field (D2); executing the obtained STORE CLOCK FAST machine instruction, the execution comprising: 1) arithmetically adding contents of the base register to the displacement field to determine a storage address; 2) obtaining the TOD clock value; and 3) storing the TOD clock value at the determined storage address. 